1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the invention relates to a metal damascene method for manufacturing a multilevel metal interconnect.
2. Description of the Related Art
Due to the increasingly high integration of ICs, chips simply cannot provide sufficient area for manufacturing interconnections. Therefore, in accord with the increased interconnects manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two metal layers. In particular, a number of multi-function products, such as microprocessors, even require 4 or 5 metal layers to complete the internal connections thereof. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent metal layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug in the semiconductor industry.
Generally, the via plug is made of tungsten or aluminum, and the wire is made of aluminum. When the wire width becomes smaller, the tungsten or aluminum via plug and aluminum wire become less appropriate, because the resistance of tungsten and aluminum seriously affect the RC time constant of the connections between the devices.
Since copper has many good qualities such as a high melting point, high electromigration resistance and low resistance, it can prove advantageous to use copper as the interconnects. Additionally, the copper wire is twice as efficient as aluminum wire. The RC delay and the static capacitance which exists between the wires can be reduced by using copper interconnects. In order to increase the integration of ICs and the transportation rate of devices, it is necessary to use copper as a multilevel metal interconnects.
FIGS. 1A through 1C are schematic, cross-sectional views of the conventional damascene process for manufacturing a multilevel metal interconnects.
As shown in FIG. 1A, a substrate 100 is provided. A wire 102 is formed on the substrate 100. A dielectric layer 104 is formed on the substrate 100 and the wire 102. A via hole 110 is formed by patterning the dielectric layer 104 to expose a portion of the wire 102.
As shown in FIG. 1B, a barrier layer 106 is formed on the dielectric layer 104 and in the via hole 110. The barrier layer 106 is used as an intermediate layer to prevent the interaction of conductive material with dielectric material. A copper layer 108 is formed on the barrier layer 106 and fills the via hole 110. The copper layer 108 can be made from copper or copper alloy.
As shown in FIG. 1C, a chemical-mechanical polishing step (CMP) is used to strip a portion of the conductive layer 108 and the barrier layer 106, and then a via plug 114 is formed in the dielectric layer 104.
Consequently, after performing a CMP step to the conductive layer 108 and the barrier layer 104, copper particles 108a are remained on the surface of the dielectric layer 104. It is often that copper particles 108a penetrate into, or even through the dielectric layer 104 to induce leakage and device failure. Furthermore, as shown in FIG. 2, a photoresist 206 is used to form a via hole. Since a portion of the photoresist 206 is worn away while performing an etching step, it leads to a sloped via hole and distortion of the pattern. The distortion of the pattern is a barrier to miniaturizing devices. Moreover, the polishing rates are different between dense and light regions of the wire and the via plug, so that while performing a chemical-mechanical polishing step to strip a portion of the conductive layer 108 and the barrier layer 106, the dense region of the wire or the via plug manifests dishing, which is an oxide recess. Thus, the uniformity is poor.